xor2 standard cell family

2-I/P exclusive OR gate
xor2 symbol
2 XOR gates designed for minimum transistor count and hence smallest size. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:(a^b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xor2_x05 2.3  70 3.85  0.67  16.8  3.7f  76  4.89  75  3.62
xor2_x1 2.3  70 3.85 1.27  30.1  6.5f  73  2.57  73  1.91
xor2_x05
 
Effort
FO4 Log.
a /\ 1.64 1.47
¯_ 2.34
b /\ 2.01 2.37
¯_ 2.04
xor2_x05 schematic xor2_x05 standard cell layout
xor2_x1
 
Effort
FO4 Log.
a /\ 1.56 1.36
¯_ 2.22
b /\ 1.92 2.26
¯_ 1.95
xor2_x1 schematic xor2_x1 standard cell layout