nr2a standard cell family

2-I/P NOR gate with inverted input
nr2a symbol
Single stage 2-I/P NOR gates with one inverted input. The output P:N ratio is about 0.77 and the stage effort on pin a is 1.2.
z:(a*b') cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vgalib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nr2av0x1 2.7  64 3.52 1.22  28.6  5.6f  78  4.49  76  1.30
nr2av0x1
 
Effort
FO4 Log.
a /\
¯_ 2.03
b /\ 1.42 1.68
¯_
nr2av0x1 schematic nr2av0x1 standard cell layout