xr2 standard cell family

 2-I/P exclusive OR gate
xr2 symbol
2 XOR gates designed with an AND-OR Invert gate and 2 input inverters. The xr2_x4 then has a large output inverter to drive the output. The xr2_x1 is a 1/2 stage 2-XOR, and the xr2_x4 is a 2/3 stage 2-XOR. Stage efforts are about 2 for the inverter driving the AND-OR-Invert, and 3.5 driving the output inverter.
q:(i1^i0) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xr2_x1 3.0  90 4.95 2.08  33.1  9.7f  83  2.91  74  1.86
xr2_x4 4.0 120 6.60 3.46  77.0  9.2f 135  0.75 160  0.59
xr2_x1
 
Effort
FO4 Log.
i0 /\ 2.31 2.90
¯_ 2.58
i1 /\ 2.24 2.85
¯_ 2.65
xr2_x1 schematic xr2_x1 standard cell layout
xr2_x4
 
Effort
FO4 Log.
i0 /\ 2.59 0.74
¯_ 2.32
i1 /\ 2.90 0.63
¯_ 2.02
xr2_x4 schematic xr2_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008