a2 standard cell family

 2-I/P AND gate
a2 symbol
2 I/P AND gate with a stage effort of about 1.8 for the a2_x2 and about 3.6 for the a2_x4.
q:(i1*i0) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i0.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
a2_x2 1.7  50 2.75 1.16  28.9  4.8f  68  1.49  96  1.15
a2_x4 2.0  60 3.30 2.08  45.2  4.6f  85  0.75 121  0.57
a2_x2
 
Effort
FO4 Log.
i0 /\
¯_ 1.54
i1 /\
¯_ 1.68
a2_x2 schematic a2_x2 standard cell layout
a2_x4
 
Effort
FO4 Log.
i0 /\
¯_ 1.65
i1 /\
¯_ 1.76
a2_x4 schematic a2_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008