a3 standard cell family

 3-I/P AND gate
a3 symbol
3 I/P AND gate designed with a stage effort of about 2.1 for the a3_x2 and about 4.2 for the a3_x4.
q:(i0*i1*i2) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
a3_x2 2.0  60 3.30 1.62  38.7  4.9f  96  1.49 125  1.17
a3_x4 2.3  70 3.85 2.31  55.3  4.8f 117  0.75 150  0.59
a3_x2
 
Effort
FO4 Log.
i0 /\
¯_ 1.75
i1 /\
¯_ 1.87
i2 /\
¯_ 1.96
a3_x2 schematic a3_x2 standard cell layout
a3_x4
 
Effort
FO4 Log.
i0 /\
¯_ 1.91
i1 /\
¯_ 2.02
i2 /\
¯_ 2.10
a3_x4 schematic a3_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008