on12 standard cell family

 2-I/P NAND gate with inverted input
on12 symbol
The on12_x1 is a single stage 2-NAND with one inverted input having a stage effort of about 1.3 and output P/N ratio of 1.7. The on12_x4 is a 2-NOR with an inverted input driving an output inverter, with stage efforts of about 1.3 and 4.4 and output P/N ratio of 2.
q:(i0*i1')' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i0.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
on12_x1 1.7  50 2.75 1.04   8.7  4.4f  47  2.99  34  1.86
on12_x4 2.7  80 4.40 2.19  57.3  3.8f 140  0.74 163  0.59
on12_x1
 
Effort
FO4 Log.
i0 /\ 1.19 1.25
¯_
i1 /\
¯_ 1.68
on12_x1 schematic on12_x1 standard cell layout
on12_x4
 
Effort
FO4 Log.
i0 /\ 2.32 0.30
¯_
i1 /\
¯_ 2.03
on12_x4 schematic on12_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008