oa2a22 standard cell family

 2×2-AND into 2-OR gate
oa2a22 symbol
2-2 I/P AND-OR gate with a stage effort of about 3.5 for the oa2a22_x2, and about 7 for the oa2a22_x4.
q:((i2*i3)+(i0*i1)) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
oa2a22_x2 3.0  90 4.95 1.39  28.7  3.6f 105  1.49 132  1.18
oa2a22_x4 3.3 100 5.50 2.08  45.9  3.5f 136  0.75 175  0.61
oa2a22_x2
 
Effort
FO4 Log.
i0 /\
¯_ 2.03
i1 /\
¯_ 1.98
i2 /\
¯_ 2.37
i3 /\
¯_ 2.43
oa2a22_x2 schematic oa2a22_x2 standard cell layout
oa2a22_x4
 
Effort
FO4 Log.
i0 /\
¯_ 2.42
i1 /\
¯_ 2.37
i2 /\
¯_ 2.77
i3 /\
¯_ 2.83
oa2a22_x4 schematic oa2a22_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008