oa22 standard cell family

 2-AND into 2-OR gate
oa22 symbol
2-1 I/P AND-OR gate with stage efforts of about 3.5 for pins i0 and i1 and 2.9 for pin i2 of the oa22_x2, and about 7 for pins i0 and i1 and 5.7 for pin i2 of the oa22_x4.
q:((i0*i1)+i2) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
oa22_x2 2.0  60 3.30 1.16  28.2  3.5f 103  1.49 136  1.18
oa22_x4 2.7  80 4.40 1.85  44.7  3.4f 133  0.75 182  0.61
oa22_x2
 
Effort
FO4 Log.
i0 /\
¯_ 2.04
i1 /\
¯_ 1.98
i2 /\
¯_ 2.06
oa22_x2 schematic oa22_x2 standard cell layout
oa22_x4
 
Effort
FO4 Log.
i0 /\
¯_ 2.45
i1 /\
¯_ 2.39
i2 /\
¯_ 2.34
oa22_x4 schematic oa22_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008