o4 standard cell family

 4-I/P OR gate
o4 symbol
4 I/P OR gate with a stage effort of about 3.4 for the o4_x2 and about 5.6 for the o4_x4.
q:(i2+i0+i1+i3) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i3.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
o4_x2 2.3  70 3.85 1.50  31.6  4.2f  86  1.49 175  1.25
o4_x4 2.7  80 4.40 2.31  68.0  5.7f 141  0.75 261  0.64
o4_x2
 
Effort
FO4 Log.
i0 /\
¯_ 2.76
i1 /\
¯_ 2.55
i2 /\
¯_ 2.87
i3 /\
¯_ 2.21
o4_x2 schematic o4_x2 standard cell layout
o4_x4
 
Effort
FO4 Log.
i0 /\
¯_ 2.75
i1 /\
¯_ 2.40
i2 /\
¯_ 2.98
i3 /\
¯_ 3.11
o4_x4 schematic o4_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008