o3 standard cell family

 3-I/P OR gate
o3 symbol
3 I/P OR gate with a stage effort of about 2.8 for the o3_x2 and about 5.7 for the o3_x4.
q:(i0+i1+i2) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
o3_x2 2.0  60 3.30 1.39  30.7  4.4f  84  1.49 145  1.20
o3_x4 2.3  70 3.85 2.08  47.4  4.2f 102  0.75 189  0.62
o3_x2
 
Effort
FO4 Log.
i0 /\
¯_ 2.36
i1 /\
¯_ 2.23
i2 /\
¯_ 1.98
o3_x2 schematic o3_x2 standard cell layout
o3_x4
 
Effort
FO4 Log.
i0 /\
¯_ 2.63
i1 /\
¯_ 2.50
i2 /\
¯_ 2.26
o3_x4 schematic o3_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008