na3 standard cell family

 3-I/P NAND gate
na3 symbol
The na3_x1 is a single stage 3-NAND with P/N ratio of about 2.3, which makes the P and N transistors the same size. The na3_x4 is a 3 stage 3-NAND with stage efforts of about 1.1 and 3.9.
nq:(i0*i1*i2)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
na3_x1 1.7  50 2.75  0.92  11.3  4.6f  52  3.00  41  2.57
na3_x4 2.7  80 4.40 2.66  61.6  4.9f 158  0.74 155  0.57
na3_x1
 
Effort
FO4 Log.
i0 /\ 1.52 1.48
¯_
i1 /\ 1.49 1.53
¯_
i2 /\ 1.41 1.50
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na3_x1 schematic na3_x1 standard cell layout
na3_x4
 
Effort
FO4 Log.
i0 /\ 2.32 0.37
¯_
i1 /\ 2.51 0.38
¯_
i2 /\ 2.43 0.38
¯_
na3_x4 schematic na3_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008