na2 standard cell family

 2-I/P NAND gate
na2 symbol
The na2_x1 is a single stage 2-NAND with P/N ratio of 1.7. The na2_x4 is a 3 stage 2-NAND with stage efforts of about 0.9 and 3.9.
nq:(i0*i1)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
na2_x1 1.3  40 2.20  0.69   8.7  4.4f  47  2.99  34  1.86
na2_x4 2.3  70 3.85 2.43  59.4  5.0f 151  0.74 133  0.57
na2_x1
 
Effort
FO4 Log.
i0 /\ 1.26 1.30
¯_
i1 /\ 1.19 1.25
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na2_x1 schematic na2_x1 standard cell layout
na2_x4
 
Effort
FO4 Log.
i0 /\ 2.11 0.38
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i1 /\ 2.22 0.39
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na2_x4 schematic na2_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008