halfadder standard cell family

 2-I/P half adder
halfadder symbol
2 I/P half adder with carry and sum outputs.
cout:(a*b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
halfadder_x2 5.3 160 8.80 3.26  79.0 10.5f  94  1.49 105  1.15
halfadder_x4 6.0 180 9.90 4.64 122.3 10.4f 121  0.75 134  0.59
sout:(a^b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
halfadder_x2 5.3 160 8.80 3.26  68.6 10.5f 129  1.49 162  1.18
halfadder_x4 6.0 180 9.90 4.64 101.9 10.4f 158  0.75 204  0.61
halfadder_x2
 
Effort
FO4 Log.
a /\ 3.27 1.59
¯_ 2.54
b /\ 2.92 1.56
¯_ 2.70
halfadder_x2 schematic halfadder_x2 standard cell layout
halfadder_x4
 
Effort
FO4 Log.
a /\ 3.39 0.81
¯_ 2.62
b /\ 3.06 0.78
¯_ 2.85
halfadder_x4 schematic halfadder_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008