inv standard cell family

 inverter
inv symbol
4 inverters with P/N ratios of 2 (inv_x1, inv_x8), 1.5 (inv_x2) and 1.7 (inv_x4). The inv_x2 is considered as the reference inverter for logical effort calculations.
nq:i' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
inv_x1 1.0  30 1.65  0.35   5.7  3.4f  40  2.98  36  2.31
inv_x2 1.0  30 1.65  0.58   8.7  5.5f  40  1.98  32  1.15
inv_x4 1.3  40 2.20 1.36  15.4 11.6f  37  0.87  31  0.57
inv_x8 2.3  70 3.85 2.77  33.2 24.6f  36  0.37  33  0.28
inv_x1
 
Effort
FO4 Log.
i /\ 1.06 1.05
¯_
inv_x1 schematic inv_x1 standard cell layout
inv_x2
 
Effort
FO4 Log.
i /\ 1.01 1.00
¯_
inv_x2 schematic inv_x2 standard cell layout
inv_x4
 
Effort
FO4 Log.
i /\ 0.97 0.98
¯_
inv_x4 schematic inv_x4 standard cell layout
inv_x8
 
Effort
FO4 Log.
i /\ 0.96 0.94
¯_
inv_x8 schematic inv_x8 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008