ao22 standard cell family

 2-OR into 2-AND gate
ao22 symbol
2-1 I/P OR-AND gate with stage efforts of about 3.5 for pins i0 and i1 and 2.6 for pin i2 of the ao22_x2, and about 7 for pins i0 and i1 and 5.2 for pin i2 of the ao22_x4.
q:((i0+i1)*i2) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
ao22_x2 2.0  60 3.30 1.27  28.7  3.6f 104  1.49 140  1.18
ao22_x4 2.7  80 4.40 1.96  45.1  3.4f 134  0.75 185  0.61
ao22_x2
 
Effort
FO4 Log.
i0 /\
¯_ 2.17
i1 /\
¯_ 2.03
i2 /\
¯_ 1.85
ao22_x2 schematic ao22_x2 standard cell layout
ao22_x4
 
Effort
FO4 Log.
i0 /\
¯_ 2.58
i1 /\
¯_ 2.42
i2 /\
¯_ 2.06
ao22_x4 schematic ao22_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008