an12 standard cell family

 2-I/P NOR gate with inverted input
an12 symbol
The an12_x1 is a single stage 2-NOR with one inverted input having a stage effort of about 1.6 and output P/N ratio of 2.3. The an12_x4 is a 2-NAND with an inverted input driving an output inverter, with stage efforts of about 1.3 and 3.6 and output P/N ratio of 2.
q:(i0+i1')' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i0.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
an12_x1 1.7  50 2.75 1.04  10.2  5.3f  44  2.92  45  2.33
an12_x4 2.7  80 4.40 2.43  57.9  3.8f 127  0.75 147  0.57
an12_x1
 
Effort
FO4 Log.
i0 /\ 1.44 1.61
¯_
i1 /\
¯_ 1.95
an12_x1 schematic an12_x1 standard cell layout
an12_x4
 
Effort
FO4 Log.
i0 /\ 2.11 0.29
¯_
i1 /\
¯_ 1.74
an12_x4 schematic an12_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008