o2 standard cell family

2-I/P OR gate
o2 symbol
2 I/P OR gate with a stage effort of about 2.2 for the o2_x2 and about 4.4 for the o2_x4.
q:(i0+i1) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
o2_x2 1.7  50 2.75 1.27  28.9  4.7f  80  1.52 113  1.22
o2_x4 2.0  60 3.30 1.96  45.0  4.5f  99  0.76 145  0.62
o2_x2
 
Effort
FO4 Log.
i0 /\
¯_ 1.91
i1 /\
¯_ 1.75
o2_x2 schematic o2_x2 standard cell layout
o2_x4
 
Effort
FO4 Log.
i0 /\
¯_ 2.07
i1 /\
¯_ 1.92
o2_x4 schematic o2_x4 standard cell layout