o3 standard cell family

3-I/P OR gate
o3 symbol
3 I/P OR gate with a stage effort of about 2.8 for the o3_x2 and about 5.7 for the o3_x4.
q:(i0+i1+i2) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
o3_x2 2.0  60 3.30 1.39  30.6  4.4f  83  1.52 149  1.25
o3_x4 2.3  70 3.85 2.08  46.7  4.2f 101  0.76 193  0.65
o3_x2
 
Effort
FO4 Log.
i0 /\
¯_ 2.39
i1 /\
¯_ 2.26
i2 /\
¯_ 2.01
o3_x2 schematic o3_x2 standard cell layout
o3_x4
 
Effort
FO4 Log.
i0 /\
¯_ 2.71
i1 /\
¯_ 2.52
i2 /\
¯_ 2.27
o3_x4 schematic o3_x4 standard cell layout