nxr2 standard cell family

2-I/P exclusive NOR gate
nxr2 symbol
2 XNOR gates designed with an AND-OR Invert gate and 2 input inverters. The nxr2_x4 then has a large output inverter to drive the output. The nxr2_x1 is a 1/2 stage 2-XNOR, and the nxr2_x4 is a 2/3 stage 2-XNOR. Stage efforts are about 2 for the inverter driving the AND-OR-Invert, and 3.5 driving the output inverter.
nq:(i1^i0)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nxr2_x1 3.0  90 4.95 2.08  32.4  9.0f  79  3.01  77  2.02
nxr2_x4 4.0 120 6.60 3.46  71.3  9.4f 135  0.76 167  0.62
nxr2_x1
 
Effort
FO4 Log.
i0 /\ 2.37 3.00
¯_ 2.59
i1 /\ 2.05 2.86
¯_ 2.77
nxr2_x1 schematic nxr2_x1 standard cell layout
nxr2_x4
 
Effort
FO4 Log.
i0 /\ 2.60 0.74
¯_ 2.38
i1 /\ 2.79 0.70
¯_ 2.29
nxr2_x4 schematic nxr2_x4 standard cell layout