no3 standard cell family

3-I/P NOR gate
no3 symbol
The no3_x1 is a single stage 3-NOR with P/N ratio of 1.5. The no3_x4 is a 3 stage 3-NOR with stage efforts of about 1.2 and 3.9.
nq:(i2+i0+i1)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
no3_x1 1.7  50 2.75  0.81  11.7  5.1f  56  4.59  48  2.29
no3_x4 2.7  80 4.40 2.54  64.0  5.5f 190  0.76 163  0.61
no3_x1
 
Effort
FO4 Log.
i0 /\ 2.02 2.15
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i1 /\ 1.75 2.06
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i2 /\ 2.13 2.17
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no3_x1 schematic no3_x1 standard cell layout
no3_x4
 
Effort
FO4 Log.
i0 /\ 2.88 0.45
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i1 /\ 2.75 0.44
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i2 /\ 2.49 0.43
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no3_x4 schematic no3_x4 standard cell layout