no4 standard cell family

 4-I/P NOR gate
no4 symbol
The no4_x1 is a single stage 4-NOR with P/N ratio of 1.1. The no4_x4 is a 3 stage 4-NOR with stage efforts of about 1.4 and 3.9.
nq:(i3+i2+i0+i1)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
no4_x1 2.0  60 3.30  0.92  12.1  5.2f  61  6.15  48  2.31
no4_x4 3.3 100 5.50 2.66  59.9  5.6f 192  0.76 154  0.61
no4_x1
 
Effort
FO4 Log.
i0 /\ 2.38 2.61
¯_
i1 /\ 2.05 2.57
¯_
i2 /\ 2.61 2.70
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i3 /\ 2.67 2.68
¯_
no4_x1 schematic no4_x1 standard cell layout
no4_x4
 
Effort
FO4 Log.
i0 /\ 3.02 0.43
¯_
i1 /\ 2.70 0.44
¯_
i2 /\ 3.24 0.44
¯_
i3 /\ 3.34 0.43
¯_
no4_x4 schematic no4_x4 standard cell layout
Web data book for the ssxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008