mxi2 standard cell family

Inverting 2-way multiplexers
mxi2 symbol
This two-way inverting mux uses a CMOS transfer gate for the fastest speed.
z:((a0*s')+(a1*s))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a0.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
rgalib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
mxi2v2x1 4.0  96 5.28 1.66  26.0  5.7f  72  2.54  53  1.57
mxi2v2x1
 
Effort
FO4 Log.
a0 /\ 1.56 1.36
¯_
a1 /\ 1.56 1.33
¯_
s /\ 1.93 2.68
¯_ 1.80
mxi2v2x1 schematic mxi2v2x1 standard cell layout