nd2 standard cell family

2-I/P NAND gate
nd2 symbol
Single stage 2-I/P NAND gates with x2 and x4 drive strengths and a P:N ratio of about 2.3. The nd2v6x2 is a layout variant of the nd2v0x2 copied from a published design by Virage Logic. It's faster, but doesn't double contacts where possible and has poorer connectivity. The nd2v6x4 is a slower layout variant of the nd2v0x4 with the series N transistors arranged differently.
z:(a*b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
rgalib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd2v0x2 1.3  32 1.76  0.88  10.6  5.2f  44  2.11  37  1.84
nd2v6x2 1.3  32 1.76  0.88  10.5  5.2f  44  2.11  36  1.84
nd2v0x4 2.7  64 3.52 1.76  20.4 10.3f  43  1.06  36  0.92
nd2v6x4 2.7  64 3.52 1.76  21.4 10.6f  44  1.06  37  0.92
nd2v0x2
 
Effort
FO4 Log.
a /\ 1.24 1.23
¯_
b /\ 1.17 1.20
¯_
nd2v0x2 schematic nd2v0x2 standard cell layout
nd2v6x2
 
Effort
FO4 Log.
a /\ 1.23 1.22
¯_
b /\ 1.16 1.19
¯_
nd2v6x2 schematic nd2v6x2 standard cell layout
nd2v0x4
 
Effort
FO4 Log.
a /\ 1.22 1.21
¯_
b /\ 1.15 1.18
¯_
nd2v0x4 schematic nd2v0x4 standard cell layout
nd2v6x4
 
Effort
FO4 Log.
a /\ 1.25 1.26
¯_
b /\ 1.18 1.22
¯_
nd2v6x4 schematic nd2v6x4 standard cell layout