oan22 standard cell family

 2×2-OR into 2-AND gate
oan22 symbol
2 cells with different drive strengths, each with a P/N ratio of about 2. The oan22_x1 has a stage effort of about 1.7 and the oan22_x2 about 2.2.
z:((a1+a2)*(b1+b2)) cell width power Generic 0.13um typical timing (ps & ps/fF), pin b2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
oan22_x1 2.7  80 4.40 1.22  21.4  4.5f  84  2.97 108  2.31
oan22_x2 2.7  80 4.40 1.93  34.5  6.4f  87  1.52 110  1.22
oan22_x1
 
Effort
FO4 Log.
a1 /\
¯_ 2.43
a2 /\
¯_ 2.28
b1 /\
¯_ 2.24
b2 /\
¯_ 2.06
oan22_x1 schematic oan22_x1 standard cell layout
oan22_x2
 
Effort
FO4 Log.
a1 /\
¯_ 2.27
a2 /\
¯_ 2.12
b1 /\
¯_ 2.09
b2 /\
¯_ 1.92
oan22_x2 schematic oan22_x2 standard cell layout
Web data book for the vxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008