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To add new cells to an existing function in the vsclib, use the following flow, explained for the aoi21v0x2. It is similar for the other libraries.

  1. Draw the cell with Graal in
    $ cd alliance/cells/vsclib
    Run makeallviews to create all the cell views that can be automatically created.
    $ ./makeallviews aoi21v0x2
  2. Go to
    $ cd magic/cif/vsclib013
    and convert the CIF file to Postscript using the script makeps
    $ ./makeps aoi21v0x2
    Convert the postscript file to a GIF file and move it to
  3. Create a PMD file
  4. Create a bash file in
    $ cd alliance/makevbe/vsclib200
    with nominal (equals guessed) characteristics compatible with the Alliance sxlib. Run the bash file and redirect the output to the VBE directory.
    $ ./aoi21v0x2.bash > aoi21v0x2.vbe
    $ mv aoi21v0x2.vbe ../../vbe/vsclib200
  5. Draw the schematic with Xcircuit in
    $ cd xcircuit/cells/vsclib
    Make a GIF file from the schematic and move it to
  6. Alter the web data book comment at
    This will appear on the data sheet.
  7. Add the new cell name to the file
    It is important that the name reflects the correct drive strength.
  8. Run command makefunction for the new cell. This creates all the Spice and characterisation scripts in directory function. Alternatively run makelib to remake all the library cells.
    $ cd magic/spice_vsclib013
    $ ./makefunction aoi21
  9. makefunction has created in directory aoi21 a file aoi21v0x2_func.cir. Run this with Winspice and check that the functionality is correct. The cell waveforms can be viewed by running aoi21v0x2_fplot.cir. You will need to do this if the functionality is reported as incorrect. The functionality comes from the logical expression in the PMD file and is compared to what the cell actually does in Spice.
  10. In directory aoi21 run allaoi21 to simulate all the aoi21 cells with Winspice and create a Liberty format .LIB file, Alliance format VBE files in
    and an html format data sheet in
    Alternatively run allcells from directory
    in order to characterise the whole library (this takes a long time). If allcells is run with an argument, then the Winspice simulation is skipped, and existing output files are used to remake the .LIB, VBE and html files.
PMD File Example for aoi21v0x2
pwidth 54
nwidth 40
unitcap 1.0
min_capacitance 2
max_capacitance 260
max_fanout 6
fanout_load 1
a1 lower_lh_pct 7
a1 upper_lh_pct 93
a2 lower_lh_pct 7
a2 upper_lh_pct 93
b lower_lh_pct 8
b upper_lh_pct 92
a1 lower_hl_pct 7
a1 upper_hl_pct 93
a2 lower_hl_pct 8
a2 upper_hl_pct 92
b lower_hl_pct 8
b upper_hl_pct 92

pwidth and nwidth are used for the leakage current calculation.

unitcap sets the load capacitances in the Lookup Table (LUT). These are the product of unitcap, the drive strength and the values of total_output_net_capacitance from the technology.pmd file.

$ more magic/spice_vsclib013/technology.pmd
total_output_net_capacitance 1 4 12 30 62 130

For the aoi21v0x2 this means 1×2×130 for the maximum load, or 260fF.

The maximum load should be set such that when both the input and output rise transitions are 1500ps, the load capacitance lies between the maximum and second largest values … between 124fF and 260fF in this case.

If for the aoi21v0x2 the unitcap is set to 1.0, then when we check the LUT we see:

timing() {
related_pin        : "a1" ;
rise_transition(x2_260_6x10) { /* 7%-93%, scaled to 0%-100% */
values( "  89.0,  125.4,  223.5,  445.7,  841.6, 1683.1", \
        " 367.2,  404.6,  500.2,  702.8, 1046.4, 1821.1" ); }

This shows that the max load is 260fF (1.0×130×2), and that the transition time at this load and an input transition time of 1500ps is 1821.1ps, which is larger than 1500ps. At the previous load of 124fF (1.0×62×2), the transition time is 1046.4ps, which is less than 1500ps. 1500ps is defined as the max allowed transition time, and we want delays at this load to be interpolated between 2 values in the LUT rather than extrapolated beyond the LUT.

The values min_capacitance, max_capacitance and fanout_load are written straight to the .LIB file, except that the max_capacitance will be reduced to the load that gives an output transition of 1500ps when the input also has a transition time of 1500ps.

The upper and lower threshold values have to be determined for each technology by test simulations. For this technology the values are listed on the threshold page.

VBE File Example for aoi21v0x2
cat $ALLIANCE_TOP/cells/sxlib/$sxlib.vbe | \
sed s/$sxlib/$cell/ | \
chpin   i0 a1  | \
chpin   i1 a2 | \
chpin   i2 b | \
chpin   nq z | \
chfield area 2880 | \
chfield rdown_a1_z 4750 | \
chfield rdown_a2_z 4750 | \
chfield rdown_b_z  4630 | \
chfield rup_a1_z   4760 | \
chfield rup_a2_z   4760 | \
chfield rup_b_z    4760 | \
chfield cin_a1 9 | \
chfield cin_a2 9 | \
chfield cin_b 9 | \
chlfield transistors 6
cat $ALLIANCE_TOP/cells/sxlib/$sxlib.vbe | \
sed s/$sxlib/$cell/ | \
chpin   i0 a1  | \
chpin   i1 a2 | \
chpin   i2 b | \
chpin   nq z | \
chfield area 5184 | \
chfield rdown_a1_z 2280 | \
chfield rdown_a2_z 2280 | \
chfield rdown_b_z  2160 | \
chfield rup_a1_z   2290 | \
chfield rup_a2_z   2290 | \
chfield rup_b_z    2290 | \
chfield cin_a1 19 | \
chfield cin_a2 19 | \
chfield cin_b 18 | \
chlfield transistors 9

In alliance/makevbe/vsclib200 an existing BASH file like the one for the aoi21v0x1 can be copied and edited for the aoi21v0x2. The only field that really needs to be updated is the area field since the other values are replaced by the values from the characterisation. But making some sort of reasonable guess for the others will allow the library to be used with pseudo Alliance 0.35µm timing.

I use a spreadsheet to link transistor widths to values of drive resistance and pin capacitance.

Winspice Logical Check with Plot Output
winspice output

The bottom line of the Winspice plot output is the expected logical response. The waveforms above it are from the extracted Spice deck, one lightly loaded and one heavily loaded. They should match the expected logical output.

If they don't match, likely causes are missing contacts, missing pieces of metal and mislabelled connectors.