or4 standard cell family

4-I/P OR gate
or4 symbol
4 I/P OR gates designed with large (v0 version), medium (v3 version) and small (v4 version) input stages. The stage effort is 1.9 for the or4v0x05, 2.2 for the or4v0x1, 2.6 for the or4v0x2, 3.3 for the or4v3x2, 2.8 for the or4v0x3 and 4.0 for the or4v4x05. The v0 cells are optimised for speed with typical wireload values, while the v4 cell is optimised for a zero wireload capacitance. The v3 is designed to have a low Prop delay and high drive but still be small by using an unfolded input NOR gate. The P/N ratio is kept to about 2 except for the or4v3x2 NOR gate which has a P/N ratio of about 1.
z:(a+b+c+d) cell width power Generic 0.13um typical timing (ps & ps/fF), pin d.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
or4v0x05 2.7  64 3.52  0.80  14.2  3.9f  82  4.96 116  4.25
or4v4x05 2.7  64 3.52  0.62  12.1  2.3f  71  4.95 171  4.58
or4v0x1 3.7  88 4.84 1.00  18.2  5.0f  90  3.30 110  2.76
or4v0x2 3.7  88 4.84 1.36  24.7  6.1f  96  2.13 107  1.81
or4v3x2 2.7  64 3.52  0.90  22.7  4.2f  82  2.13 141  1.90
or4v0x3 4.0  96 5.28 1.71  30.3  6.9f  98  1.49 109  1.27
or4v0x05
 
Effort
FO4 Log.
a /\
¯_ 3.09
b /\
¯_ 2.98
c /\
¯_ 2.75
d /\
¯_ 2.46
or4v0x05 schematic or4v0x05 standard cell layout
or4v4x05
 
Effort
FO4 Log.
a /\
¯_ 2.88
b /\
¯_ 2.82
c /\
¯_ 2.62
d /\
¯_ 2.37
or4v4x05 schematic or4v4x05 standard cell layout
or4v0x1
 
Effort
FO4 Log.
a /\
¯_ 3.20
b /\
¯_ 2.99
c /\
¯_ 2.70
d /\
¯_ 2.30
or4v0x1 schematic or4v0x1 standard cell layout
or4v0x2
 
Effort
FO4 Log.
a /\
¯_ 3.10
b /\
¯_ 2.89
c /\
¯_ 2.58
d /\
¯_ 2.14
or4v0x2 schematic or4v0x2 standard cell layout
or4v3x2
 
Effort
FO4 Log.
a /\
¯_ 2.68
b /\
¯_ 2.59
c /\
¯_ 2.38
d /\
¯_ 2.08
or4v3x2 schematic or4v3x2 standard cell layout
or4v0x3
 
Effort
FO4 Log.
a /\
¯_ 2.97
b /\
¯_ 2.77
c /\
¯_ 2.46
d /\
¯_ 2.03
or4v0x3 schematic or4v0x3 standard cell layout