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3 I/P OR gates designed with large (v0 version), medium (v3 version)
and small (v4 version) input stages. The stage effort is 1.8 for the
or3v0x05, 2.1 for the or3v0x1, 2.4 for the or3v0x2, 2.5 for the or3v3x2,
2.8 for the or3v0x4 and 4.0 for the or3v4x05. The v0 cells are optimised
for speed with typical wireload values, while the v4 cell is optimised
for a zero wireload capacitance. The v3 is designed to have a low Prop
delay and high drive but still be small by using an unfolded input NOR gate.
The P/N ratio is kept to about 2 except for the or3v3x2 NOR gate which
has a P/N ratio of about 1.3. |