oai21a2 standard cell family

2-OR with one inverted input into 2-NAND
oai21a2 symbol
Two cells with a P/N ratio of about 2 on the a1 and b inputs, and a stage gain of about 1.4 (x05) and 1.7 (x1) on the a2 input.
z:((a1+a2')*b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
oai21a2v0x05 2.7  64 3.52  0.54  14.8  2.2f  87  7.31  91  5.31
oai21a2v0x1 2.7  64 3.52  0.92  23.8  3.3f  86  4.18  89  2.87
oai21a2v0x05
 
Effort
FO4 Log.
a1 /\ 1.89 1.98
¯_
a2 /\
¯_ 2.08
b /\ 1.32 1.34
¯_
oai21a2v0x05 schematic oai21a2v0x05 standard cell layout
oai21a2v0x1
 
Effort
FO4 Log.
a1 /\ 1.81 1.93
¯_
a2 /\
¯_ 1.92
b /\ 1.26 1.29
¯_
oai21a2v0x1 schematic oai21a2v0x1 standard cell layout