oai21 standard cell family

2-OR into 2-NAND gate
oai21 symbol
7 single stage cells with different drive strengths, each with a P/N ratio of about 2. The width of the P-transistor connected to pin b is designed to have a similar conductivity to the two series P-transistors in order to keep a consistent output drive capability.
z:((a1+a2)*b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
oai21v0x05 1.7  40 2.20  0.36   7.1  2.7f  63  7.28  47  5.31
oai21v0x1 1.7  40 2.20  0.61  10.9  4.3f  59  4.30  43  3.11
oai21v0x2 2.7  64 3.52 1.32  21.9  7.9f  58  2.08  47  1.54
oai21v0x3 3.7  88 4.84 1.72  28.2 11.8f  57  1.55  41  1.10
oai21v0x4 4.3 104 5.72 2.41  38.7 15.9f  57  1.12  41  0.78
oai21v0x6 6.3 152 8.36 3.63  57.2 24.3f  55  0.73  40  0.53
oai21v0x8 8.0 192 10.56 4.87  76.0 33.3f  55  0.54  40  0.40
oai21v0x05
 
Effort
FO4 Log.
a1 /\ 1.87 1.95
¯_
a2 /\ 1.75 1.97
¯_
b /\ 1.36 1.39
¯_
oai21v0x05 schematic oai21v0x05 standard cell layout
oai21v0x1
 
Effort
FO4 Log.
a1 /\ 1.79 1.90
¯_
a2 /\ 1.65 1.87
¯_
b /\ 1.27 1.30
¯_
oai21v0x1 schematic oai21v0x1 standard cell layout
oai21v0x2
 
Effort
FO4 Log.
a1 /\ 1.79 1.82
¯_
a2 /\ 1.58 1.68
¯_
b /\ 1.27 1.31
¯_
oai21v0x2 schematic oai21v0x2 standard cell layout
oai21v0x3
 
Effort
FO4 Log.
a1 /\ 1.75 1.87
¯_
a2 /\ 1.60 1.82
¯_
b /\ 1.18 1.17
¯_
oai21v0x3 schematic oai21v0x3 standard cell layout
oai21v0x4
 
Effort
FO4 Log.
a1 /\ 1.75 1.88
¯_
a2 /\ 1.57 1.77
¯_
b /\ 1.17 1.16
¯_
oai21v0x4 schematic oai21v0x4 standard cell layout
oai21v0x6
 
Effort
FO4 Log.
a1 /\ 1.75 1.90
¯_
a2 /\ 1.56 1.79
¯_
b /\ 1.16 1.14
¯_
oai21v0x6 schematic oai21v0x6 standard cell layout
oai21v0x8
 
Effort
FO4 Log.
a1 /\ 1.76 1.92
¯_
a2 /\ 1.57 1.81
¯_
b /\ 1.15 1.13
¯_
oai21v0x8 schematic oai21v0x8 standard cell layout