nr3 standard cell family

3-I/P NOR gate
nr3 symbol
The fastest speed occurs when the shape factor r=√( KP÷ KN×µ). For a 3-NOR gate, we use KP=22/8; KN=1, and µ=9/4, which gives r=√(99/16)≈2.5. This gives a P/N ratio of γ=0.9 which is lower than γ=1 which we want to set as the minimum. For the fastest gates then we will use P/N=1 which gives a shape factor r=√=22/8=2.75. This value has been used for the v1 version, which are fast with unbalanced output skews. The P/N ratio has been kept as close to 2 as possible for the v0 version in order to give more balanced output skews, even if this is not the fastest configuration.
z:(a+b+c)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nr3v0x05 1.7  40 2.20  0.53   7.2  3.7f  51  6.23  48  3.88
nr3v1x05 1.7  40 2.20  0.67   8.3  4.2f  56  6.24  38  2.39
nr3v0x1 2.7  64 3.52  0.99  11.5  7.0f  44  3.12  47  2.33
nr3v0x2 3.7  88 4.84 1.46  17.3 10.4f  46  2.16  48  1.55
nr3v0x3 4.7 112 6.16 1.72  21.0 12.8f  44  1.69  47  1.22
nr3v0x4 5.7 136 7.48 2.45  27.2 17.4f  45  1.32  47  0.97
nr3v0x05
 
Effort
FO4 Log.
a /\ 2.17 2.28
¯_
b /\ 2.04 2.22
¯_
c /\ 1.78 2.17
¯_
nr3v0x05 schematic nr3v0x05 standard cell layout
nr3v1x05
 
Effort
FO4 Log.
a /\ 2.02 2.17
¯_
b /\ 1.93 2.13
¯_
c /\ 1.71 2.09
¯_
nr3v1x05 schematic nr3v1x05 standard cell layout
nr3v0x1
 
Effort
FO4 Log.
a /\ 2.27 2.48
¯_
b /\ 2.07 2.35
¯_
c /\ 1.74 2.20
¯_
nr3v0x1 schematic nr3v0x1 standard cell layout
nr3v0x2
 
Effort
FO4 Log.
a /\ 2.18 2.33
¯_
b /\ 2.04 2.28
¯_
c /\ 1.78 2.25
¯_
nr3v0x2 schematic nr3v0x2 standard cell layout
nr3v0x3
 
Effort
FO4 Log.
a /\ 2.21 2.38
¯_
b /\ 2.04 2.29
¯_
c /\ 1.71 2.16
¯_
nr3v0x3 schematic nr3v0x3 standard cell layout
nr3v0x4
 
Effort
FO4 Log.
a /\ 2.20 2.39
¯_
b /\ 2.07 2.35
¯_
c /\ 1.80 2.32
¯_
nr3v0x4 schematic nr3v0x4 standard cell layout