nr2a standard cell family

2-I/P NOR gate with inverted input
nr2a symbol
Single stage 2-I/P NOR gates with one inverted input. 6 drive strengths with a P/N ratio of 1 for the nr2v1x05 and 2 for the bigger drive strengths and the input inverter. The stage efforts for the non-inverting input are 1.3, 1.6, 2.1, 2.3, 2.6, and 2.9 for the x05, x1, x2, x3, x4 and x6 cells respectively.
z:(a*b') cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nr2av1x05 2.0  48 2.64  0.57   4.9  2.8f  52  7.75  33  2.97
nr2av0x1 2.0  48 2.64  0.73   6.8  4.0f  44  4.15  41  2.89
nr2av0x2 2.3  56 3.08 1.41  10.9  7.6f  40  2.08  38  1.55
nr2av0x3 3.0  72 3.96 1.58  15.3 10.4f  41  1.55  39  1.14
nr2av0x4 4.3 104 5.72 2.65  22.2 15.3f  40  1.04  38  0.77
nr2av0x6 5.7 136 7.48 3.81  33.1 22.9f  40  0.69  38  0.52
nr2av1x05
 
Effort
FO4 Log.
a /\
¯_ 1.98
b /\ 1.46 1.73
¯_
nr2av1x05 schematic nr2av1x05 standard cell layout
nr2av0x1
 
Effort
FO4 Log.
a /\
¯_ 1.89
b /\ 1.42 1.65
¯_
nr2av0x1 schematic nr2av0x1 standard cell layout
nr2av0x2
 
Effort
FO4 Log.
a /\
¯_ 1.77
b /\ 1.34 1.60
¯_
nr2av0x2 schematic nr2av0x2 standard cell layout
nr2av0x3
 
Effort
FO4 Log.
a /\
¯_ 1.75
b /\ 1.38 1.64
¯_
nr2av0x3 schematic nr2av0x3 standard cell layout
nr2av0x4
 
Effort
FO4 Log.
a /\
¯_ 1.72
b /\ 1.35 1.61
¯_
nr2av0x4 schematic nr2av0x4 standard cell layout
nr2av0x6
 
Effort
FO4 Log.
a /\
¯_ 1.74
b /\ 1.35 1.61
¯_
nr2av0x6 schematic nr2av0x6 standard cell layout