nd3ab standard cell family

3-I/P NAND gate with two inverted inputs
nd3ab symbol
Minimum size 3-I/P NAND gate with 2 inverted inputs, made from a 2-I/P NOR followed by a 2-I/P NAND. The output P/N ratio is about 2, and the gain from inputs a and b is about 1.4.
z:(a'*b'*c)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd3abv0x05 2.0  48 2.64  0.58   3.6  2.0f  48  7.42  36  5.29
nd3abv0x05
 
Effort
FO4 Log.
a /\
¯_ 2.42
b /\
¯_ 2.23
c /\ 1.31 1.45
¯_
nd3abv0x05 schematic nd3abv0x05 standard cell layout