nd3a standard cell family

3-I/P NAND gate with inverted input
nd3a symbol
Minimum size 3-I/P NAND gate with an inverted input. The output P/N ratio is about 2.3, and the gain from input a is about 1.3.
z:(a'*b*c)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd3av0x05 2.3  56 3.08  0.67   5.7  2.3f  52  5.94  41  5.09
nd3av0x05
 
Effort
FO4 Log.
a /\
¯_ 2.09
b /\ 1.53 1.60
¯_
c /\ 1.40 1.50
¯_
nd3av0x05 schematic nd3av0x05 standard cell layout