nd2ab standard cell family

2-I/P OR gate
nd2ab symbol
The nd2ab gates are 2-OR gates made up as 2 inverters driving a NAND gate. According to the theory of logical effort, this combination should be faster than a regular or2 gate, and it is. The speed can be compared to the or2 gates, especially the or2v0x1 which has the same output P-transistor size as the nd2abv0x1. The nd2ab gates are bigger and consume more power than the or2 gates.
z:(a+b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd2abv0x05 2.3  56 3.08  0.60  12.4  2.6f  70  4.96  77  3.70
nd2abv0x1 2.3  56 3.08 1.12  16.9  3.0f  68  3.31  78  2.47
nd2abv0x2 2.3  56 3.08 1.41  21.1  3.4f  71  2.48  78  1.85
nd2abv0x3 3.0  72 3.96 2.33  35.6  4.8f  74  1.35  83  1.03
nd2abv0x4 4.0  96 5.28 2.89  45.4  5.4f  78  1.07  85  0.78
nd2abv0x05
 
Effort
FO4 Log.
a /\
¯_ 1.71
b /\
¯_ 1.69
nd2abv0x05 schematic nd2abv0x05 standard cell layout
nd2abv0x1
 
Effort
FO4 Log.
a /\
¯_ 1.59
b /\
¯_ 1.55
nd2abv0x1 schematic nd2abv0x1 standard cell layout
nd2abv0x2
 
Effort
FO4 Log.
a /\
¯_ 1.56
b /\
¯_ 1.49
nd2abv0x2 schematic nd2abv0x2 standard cell layout
nd2abv0x3
 
Effort
FO4 Log.
a /\
¯_ 1.53
b /\
¯_ 1.45
nd2abv0x3 schematic nd2abv0x3 standard cell layout
nd2abv0x4
 
Effort
FO4 Log.
a /\
¯_ 1.52
b /\
¯_ 1.45
nd2abv0x4 schematic nd2abv0x4 standard cell layout