nd2a standard cell family

2-I/P NAND gate with inverted input
nd2a symbol
Single stage 2-I/P NAND gates with one inverted input. 7 drive strengths with a P/N ratio of about 2. The stage efforts for pin a are 1.1, 1.4, 1.8, 2.1, 2.3, 2.6 and 2.8 for the nd2av0x05, x1, x2, x3, x4, x6 and x8 respectively.
z:(a+b') cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd2av0x05 1.7  40 2.20  0.47   3.4  1.9f  46  7.41  35  5.30
nd2av0x1 1.7  40 2.20  0.70   5.5  3.2f  45  4.24  34  3.10
nd2av0x2 2.0  48 2.64 1.09   8.6  4.8f  43  2.47  34  1.95
nd2av0x3 2.7  64 3.52 1.56  12.7  7.2f  43  1.65  33  1.23
nd2av0x4 2.7  64 3.52 2.04  16.2  9.5f  42  1.23  32  0.93
nd2av0x6 4.0  96 5.28 3.05  24.8 14.6f  43  0.82  33  0.62
nd2av0x8 4.7 112 6.16 3.90  32.2 19.1f  42  0.62  32  0.46
nd2av0x05
 
Effort
FO4 Log.
a /\
¯_ 1.93
b /\ 1.28 1.42
¯_
nd2av0x05 schematic nd2av0x05 standard cell layout
nd2av0x1
 
Effort
FO4 Log.
a /\
¯_ 1.70
b /\ 1.23 1.37
¯_
nd2av0x1 schematic nd2av0x1 standard cell layout
nd2av0x2
 
Effort
FO4 Log.
a /\
¯_ 1.56
b /\ 1.16 1.23
¯_
nd2av0x2 schematic nd2av0x2 standard cell layout
nd2av0x3
 
Effort
FO4 Log.
a /\
¯_ 1.55
b /\ 1.14 1.21
¯_
nd2av0x3 schematic nd2av0x3 standard cell layout
nd2av0x4
 
Effort
FO4 Log.
a /\
¯_ 1.53
b /\ 1.12 1.20
¯_
nd2av0x4 schematic nd2av0x4 standard cell layout
nd2av0x6
 
Effort
FO4 Log.
a /\
¯_ 1.49
b /\ 1.14 1.22
¯_
nd2av0x6 schematic nd2av0x6 standard cell layout
nd2av0x8
 
Effort
FO4 Log.
a /\
¯_ 1.50
b /\ 1.12 1.21
¯_
nd2av0x8 schematic nd2av0x8 standard cell layout