cgn2 standard cell family

carry generator non-inverting
cgn2 symbol
The output is the carry of bits a and b and carry input c, with the delay from pin c being favoured. The cgn2_x1 has a stage effort of about 1.7 and the cgn2_x2 about 2.2.
z:((a*b)+(a*c)+(b*c)) cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
cgn2_x1 2.7  80 4.40 1.22  23.0  4.6f  92  2.97 114  2.34
cgn2_x2 2.7  80 4.40 1.93  36.5  6.2f  96  1.56 117  1.23
cgn2_x3 5.0 150 8.25 2.70  51.3  8.2f  100  1.06 119  0.78
cgn2_x4 5.0 150 8.25 3.37  62.4  9.6f  98  0.80 121  0.65
cgn2_x1
 
Effort
FO4 Log.
a /\
¯_ 2.85
b /\
¯_ 2.93
c /\
¯_ 2.18
cgn2_x1 schematic cgn2_x1 standard cell layout
cgn2_x2
 
Effort
FO4 Log.
a /\
¯_ 2.58
b /\
¯_ 2.63
c /\
¯_ 2.02
cgn2_x2 schematic cgn2_x2 standard cell layout
cgn2_x3
 
Effort
FO4 Log.
a /\
¯_ 2.58
b /\
¯_ 2.53
c /\
¯_ 2.00
cgn2_x3 schematic cgn2_x3 standard cell layout
cgn2_x4
 
Effort
FO4 Log.
a /\
¯_ 2.53
b /\
¯_ 2.48
c /\
¯_ 1.98
cgn2_x4 schematic cgn2_x4 standard cell layout