bf1 standard cell family

non-inverting buffer
bf1 symbol
A minimum set of 3 buffers has been included. The output drive strength has been maintained as an x2, with different first stage transistor sizes to give a choice of input capacitance loading and delay.
z:a cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
bf1_w05 1.0  30 1.65  0.35   9.0  2.1f  59  6.58  79  3.81
bf1_y05 1.3  40 2.20  0.42  10.7  2.5f  63  4.94  76  3.81
bf1_x1 1.3  40 2.20  0.69  16.5  3.9f  59  2.96  72  2.27
bf1_w2 1.3  40 2.20 1.32  29.2  7.0f  56  1.56  69  1.20
bf1_y1 1.3  40 2.20  0.55  14.5  2.4f  70  2.96  85  2.29
bf1_x2 1.3  40 2.20 1.11  26.3  4.9f  63  1.56  77  1.20
bf1_y2 1.3  40 2.20  0.87  23.0  2.3f  85  1.56 105  1.21
bf1_x4 1.7  50 2.75 1.98  44.6  6.9f  66  0.78  82  0.60
bf1_x8 3.0  90 4.95 3.62  81.1 11.3f  67  0.41  83  0.32
bf1_w05
 
Effort
FO4 Log.
a /\
¯_ 1.61
bf1_w05 schematic bf1_w05 standard cell layout
bf1_y05
 
Effort
FO4 Log.
a /\
¯_ 1.62
bf1_y05 schematic bf1_y05 standard cell layout
bf1_x1
 
Effort
FO4 Log.
a /\
¯_ 1.52
bf1_x1 schematic bf1_x1 standard cell layout
bf1_w2
 
Effort
FO4 Log.
a /\
¯_ 1.45
bf1_w2 schematic bf1_w2 standard cell layout
bf1_y1
 
Effort
FO4 Log.
a /\
¯_ 1.47
bf1_y1 schematic bf1_y1 standard cell layout
bf1_x2
 
Effort
FO4 Log.
a /\
¯_ 1.38
bf1_x2 schematic bf1_x2 standard cell layout
bf1_y2
 
Effort
FO4 Log.
a /\
¯_ 1.55
bf1_y2 schematic bf1_y2 standard cell layout
bf1_x4
 
Effort
FO4 Log.
a /\
¯_ 1.33
bf1_x4 schematic bf1_x4 standard cell layout
bf1_x8
 
Effort
FO4 Log.
a /\
¯_ 1.31
bf1_x8 schematic bf1_x8 standard cell layout