aon22 standard cell family
2×2-AND into 2-OR gate
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2 cells with different drive strengths, each with a P/N ratio of about 2. The aon22_x1 has a stage effort of about 1.7 and the aon22_x2 about 2.2.
z:((a1*a2)+(b1*b2))
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
b2
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
aon22_x1
2.7
80
4.40
1.22
20.6
4.6f
84
2.97
101
2.31
aon22_x2
3.0
90
4.95
1.93
32.7
6.4f
87
1.56
103
1.21
aon22_x1
Effort
FO4
Log.
a1
/\
¯_
2.43
a2
/\
¯_
2.40
b1
/\
¯_
2.09
b2
/\
¯_
2.03
aon22_x2
Effort
FO4
Log.
a1
/\
¯_
2.29
a2
/\
¯_
2.25
b1
/\
¯_
1.93
b2
/\
¯_
1.87
Web data book for the vxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2008 Graham Petley. 11 JAN 2008