xooi21 standard cell family

 2-I/P exclusive NOR gate with 2-OR input
xooi21 symbol
3 XNOR gates with OR gate input designed for minimum transistor count and hence smallest size. The OR gate is made by changing the inverter on the a input of a 2-XNOR gate into a 2-NOR gate. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:((a1+a2)^b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xooi21v0x05 3.0  72 3.96  0.87  18.6  3.5f  99  6.33  100  4.75
xooi21v0x1 4.0  96 5.28 1.52  28.1  6.0f  90  3.75  90  2.50
xooi21v0x2 6.7 160 8.80 2.73  54.2 10.8f  89  1.96  90  1.26
xooi21v0x05
 
Effort
FO4 Log.
a1 /\ 2.29 1.93
¯_ 3.10
a2 /\ 2.12 1.87
¯_ 2.98
b /\ 2.37 3.04
¯_ 2.61
xooi21v0x05 schematic xooi21v0x05 standard cell layout
xooi21v0x1
 
Effort
FO4 Log.
a1 /\ 2.24 2.05
¯_ 2.92
a2 /\ 2.02 1.87
¯_ 2.72
b /\ 2.23 2.90
¯_ 2.43
xooi21v0x1 schematic xooi21v0x1 standard cell layout
xooi21v0x2
 
Effort
FO4 Log.
a1 /\ 2.15 1.87
¯_ 2.70
a2 /\ 1.99 1.80
¯_ 2.59
b /\ 2.27 3.06
¯_ 2.39
xooi21v0x2 schematic xooi21v0x2 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008