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The cells are made from a 2-XNOR gate and a 2-XOR gate. The a and b inputs are xnored and input to a 2-XOR gate with input c. Inputs a and b have 2 to 4 stage delays, and input c has 1 or 2 stage delays. The xnr3v1x05 is made from an xnr2v0x05 and xor2v0x05; the xnr3v1x1 from an xnr2v0x1 and xor2v0x1; the xnr3v1x2 from an xnr2v0x1 and xor2v0x2.
This configuration is faster and smaller than making the function with 3 series P and N transistors driving the output. The delay shown is from pin b, while pin c is the fastest input.
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