dly2 standard cell family

 non-inverting delay cells
dly2 symbol
The dly2 cells use two inverters with series transistors. The layout style maximises internal node parasitic capacitances.
z:a cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
dly2v0x05 2.7  64 3.52  0.31  15.1  2.1f 158  8.82 202  7.00
dly2v0x1 2.7  64 3.52  0.54  23.5  2.0f 199  3.49 249  2.92
dly2v0x05
 
Effort
FO4 Log.
a /\
¯_ 3.55
dly2v0x05 schematic dly2v0x05 standard cell layout
dly2v0x1
 
Effort
FO4 Log.
a /\
¯_ 3.58
dly2v0x1 schematic dly2v0x1 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008