bsi2 vsclib013 standard cell family

bsi2 standard cell family

2 bit inverting barrel shifter

32-bit barrel shifter made with:
	gates	pins	delay
mxi2v0x1	427	640	468
mxi2v2x1	480	640	441
bsi2v2x1	373	400	418

2 bit inverting barrel shifter. When select pin s is low, the inverse of input a0 is routed to output z0 and a1 to z1. when the select pin s is high, then z0 is the inverse of a1 and z1 is the inverse of a0.
The advantage of using this cell instead of 2 inverting muxes is the reduced capacitance of pins a0 and a1. For example, a 32-bit barrel shifter, with 5 cells in sequence, has a smaller average delay, as shown on the right. It's also smaller and has fewer pins.

z0:((a0*s')+(a1*s))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a0.

leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)

vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF

bsi2v2x1 4.7 112 6.16 1.12 18.1 3.6f 69 3.69 65 2.94

z1:((a1*s')+(a0*s))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a0.

leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)

vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF

bsi2v2x1 4.7 112 6.16 1.12 18.2 3.6f 71 3.69 63 2.94

bsi2v2x1

		Effort
		FO4	Log.
a0	`/\`	1.65	1.39
a0	`¯_`
a1	`/\`	1.68	1.48
a1	`¯_`
s	`/\`	2.43	3.58
s	`¯_`	2.62