aon21b standard cell family

 2-AND into 2-OR gate, inverted input
aon21b symbol
5 cells with different drive strengths, each with a P/N ratio of about 2. The function is made from 2 2-I/P NAND gates as this gives the lowest logical effort. The stage effort for the non-inverting inputs a1 and a2 is 1.1 for the aon21bv0x05, 1.4 for the aon21bv0x1, 1.7 for the aon21bv0x2, 2.0 for the aon21bv0x3 and 2.2 for the aon21bv0x4. These stage efforts are optimised for speed with typical wireload values.
z:((a1*a2)+b') cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
aon21bv0x05 2.3  56 3.08  0.55  11.3  2.2f  85  7.42  87  5.28
aon21bv0x1 2.3  56 3.08  0.96  20.1  3.6f  76  4.24  92  3.09
aon21bv0x2 2.3  56 3.08 1.44  29.8  4.7f  78  2.47  94  1.85
aon21bv0x3 3.0  72 3.96 1.92  36.7  5.3f  82  1.75  88  1.32
aon21bv0x4 4.0  96 5.28 2.61  49.3  7.1f  82  1.24  88  0.92
aon21bv0x05
 
Effort
FO4 Log.
a1 /\
¯_ 2.12
a2 /\
¯_ 2.03
b /\ 1.33 1.48
¯_
aon21bv0x05 schematic aon21bv0x05 standard cell layout
aon21bv0x1
 
Effort
FO4 Log.
a1 /\
¯_ 1.89
a2 /\
¯_ 1.96
b /\ 1.22 1.33
¯_
aon21bv0x1 schematic aon21bv0x1 standard cell layout
aon21bv0x2
 
Effort
FO4 Log.
a1 /\
¯_ 1.73
a2 /\
¯_ 1.82
b /\ 1.16 1.23
¯_
aon21bv0x2 schematic aon21bv0x2 standard cell layout
aon21bv0x3
 
Effort
FO4 Log.
a1 /\
¯_ 1.76
a2 /\
¯_ 1.68
b /\ 1.14 1.21
¯_
aon21bv0x3 schematic aon21bv0x3 standard cell layout
aon21bv0x4
 
Effort
FO4 Log.
a1 /\
¯_ 1.73
a2 /\
¯_ 1.66
b /\ 1.12 1.19
¯_
aon21bv0x4 schematic aon21bv0x4 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008