aoi112 standard cell family

 2-AND into 3-NOR gate
aoi112 symbol
1 cell with a P/N ratio of about 2. The function is the same as the aoi211, but with the parallel P-transistors next to the output node rather than the VDD connection which gives a slower cell.
z:((c1*c2)+a+b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
aoi112v0x05 2.0  48 2.64  0.57   9.1  4.0f  55  6.26  53  4.13
aoi112v0x05
 
Effort
FO4 Log.
a /\ 2.38 2.18
¯_
b /\ 2.25 2.15
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c1 /\ 2.00 2.44
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c2 /\ 1.96 2.42
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aoi112v0x05 schematic aoi112v0x05 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008