xor2 standard cell family

2-I/P exclusive OR gate
xor2 symbol
2-input XOR gate with output P/N ratio of about 1.28. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:(a^b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vgalib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xor2v0x1 4.0  96 5.28 1.22  28.7  5.3f  84  3.63  75  1.85
FO4 Log.
a /\ 1.61 1.32
¯_ 2.36
b /\ 2.38 2.99
¯_ 2.06
xor2v0x1 schematic xor2v0x1 standard cell layout