iv1 standard cell family

inverter
iv1 symbol
There are five inverters with drive strengths from x2 to x12 and a P:N ratio of 1.44. The effort tables show the effort relative to the reference inverter in the vsclib, the iv1v2x2, which has a P:N ratio of 2.25.
z:a' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vgalib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
iv1v0x2 1.3  32 1.76  0.51   9.8  5.0f  44  2.27  34  1.27
iv1v0x4 1.3  32 1.76 1.02  12.5  9.8f  38  1.13  30  0.64
iv1v0x6 2.7  64 3.52 1.52  22.1 14.5f  40  0.76  31  0.43
iv1v0x8 2.7  64 3.52 2.03  24.8 19.2f  38  0.56  30  0.32
iv1v0x12 4.0  96 5.28 3.05  32.4 27.9f  36  0.38  33  0.32
iv1v0x2
 
Effort
FO4 Log.
a /\ 1.06 1.03
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iv1v0x2 schematic iv1v0x2 standard cell layout
iv1v0x4
 
Effort
FO4 Log.
a /\ 0.98 1.01
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iv1v0x4 schematic iv1v0x4 standard cell layout
iv1v0x6
 
Effort
FO4 Log.
a /\ 1.00 1.00
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iv1v0x6 schematic iv1v0x6 standard cell layout
iv1v0x8
 
Effort
FO4 Log.
a /\ 0.97 0.99
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iv1v0x8 schematic iv1v0x8 standard cell layout
iv1v0x12
 
Effort
FO4 Log.
a /\ 1.06 1.13
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iv1v0x12 schematic iv1v0x12 standard cell layout