nxr2 standard cell family

 2-I/P exclusive NOR gate
nxr2 symbol
2 XNOR gates designed with an AND-OR Invert gate and 2 input inverters. The nxr2_x4 then has a large output inverter to drive the output. The nxr2_x1 is a 1/2 stage 2-XNOR, and the nxr2_x4 is a 2/3 stage 2-XNOR. Stage efforts are about 2 for the inverter driving the AND-OR-Invert, and 3.5 driving the output inverter.
nq:(i1^i0)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nxr2_x1 3.0  90 4.95 2.08  33.4  9.3f  78  2.91  76  1.86
nxr2_x4 4.0 120 6.60 3.46  72.7  9.6f 132  0.75 165  0.59
nxr2_x1
 
Effort
FO4 Log.
i0 /\ 2.30 2.90
¯_ 2.58
i1 /\ 2.02 2.81
¯_ 2.72
nxr2_x1 schematic nxr2_x1 standard cell layout
nxr2_x4
 
Effort
FO4 Log.
i0 /\ 2.59 0.74
¯_ 2.33
i1 /\ 2.77 0.69
¯_ 2.24
nxr2_x4 schematic nxr2_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008