no3 standard cell family

 3-I/P NOR gate
no3 symbol
The no3_x1 is a single stage 3-NOR with P/N ratio of 1.5. The no3_x4 is a 3 stage 3-NOR with stage efforts of about 1.2 and 3.9.
nq:(i2+i0+i1)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
no3_x1 1.7  50 2.75  0.81  11.7  5.3f  54  4.38  48  2.33
no3_x4 2.7  80 4.40 2.54  64.8  5.7f 187  0.74 166  0.57
no3_x1
 
Effort
FO4 Log.
i0 /\ 2.02 2.15
¯_
i1 /\ 1.74 2.06
¯_
i2 /\ 2.13 2.17
¯_
no3_x1 schematic no3_x1 standard cell layout
no3_x4
 
Effort
FO4 Log.
i0 /\ 2.88 0.45
¯_
i1 /\ 2.74 0.44
¯_
i2 /\ 2.48 0.43
¯_
no3_x4 schematic no3_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008