nmx2 standard cell family

 Inverting 2-way multiplexers
nmx2 symbol
The nmx2_x1 is a single stage inverting mux with a P/N ratio of 1.7. The control signal cmd can be 1 or 2 delay stages with a stage effort of about 2. The nmx2_x4 is a 3 stage inverting mux with stage efforts of about 1.7 and 3.9. The control signal cmd can have 3 or 4 stages with stage efforts of about 1, 1.7 and 3.9.
nq:((i0*cmd')+(i1*cmd))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i0.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nmx2_x1 2.3  70 3.85 1.73  22.9  6.7f  70  2.92  52  1.87
nmx2_x4 4.0 120 6.60 2.77  61.5  3.8f 200  0.74 179  0.57
nmx2_x1
 
Effort
FO4 Log.
cmd /\ 1.96 2.77
¯_ 2.40
i0 /\ 1.79 1.87
¯_
i1 /\ 1.78 1.82
¯_
nmx2_x1 schematic nmx2_x1 standard cell layout
nmx2_x4
 
Effort
FO4 Log.
cmd /\ 2.91 0.67
¯_ 3.50
i0 /\ 2.86 0.29
¯_
i1 /\ 2.87 0.29
¯_
nmx2_x4 schematic nmx2_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008