nao22 standard cell family

 2-OR into 2-NAND gate
nao22 symbol
The nao22_x1 is a single stage OR-AND-Invert with P/N ratio of 1.7 for pins i0 and i1, and about 3.3 for pin i2. The nao22_x4 is a 3 stage OR-AND-Invert with stage efforts of about 1.7 and 3.9 for pins i0 and i1, and 1.3 and 3.9 for pin i2.
nq:((i0+i1)*i2)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nao22_x1 2.0  60 3.30 1.16  14.4  6.3f  54  2.92  43  1.86
nao22_x4 3.3 100 5.50 2.31  55.8  3.6f 174  0.74 162  0.57
nao22_x1
 
Effort
FO4 Log.
i0 /\ 1.70 1.76
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i1 /\ 1.55 1.74
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i2 /\ 1.32 1.25
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nao22_x1 schematic nao22_x1 standard cell layout
nao22_x4
 
Effort
FO4 Log.
i0 /\ 2.70 0.27
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i1 /\ 2.54 0.28
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i2 /\ 2.43 0.29
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nao22_x4 schematic nao22_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008